Layout Engineer

About the Role

We are seeking a highly skilled Layout Engineer to join our Library Group within the Central Engineering Group. This role focuses on circuit design related to memory, input/output (I/O), and standard cells layout.

Key Responsibilities

• Apply and ensure adherence to all necessary layout guidelines, including those for standard cells, I/O, and memory circuits.
• Understand and implement new process rules and technical requirements to produce high-quality layouts.
• Manage scheduling and floor-planning tasks for layout projects.
• Complete layouts and verification activities within planned timelines, independently managing tasks for experienced engineers.
• Quickly adopt new methodologies and openly communicate and collaborate with library team members.

Required Skills and Experience

• Minimum of 2 to 3 years of strong layout engineering experience, especially in submicron processes such as 16nm, 7nm, 5nm, 2nm, 1.4nm, and below.
• Proficiency with Cadence layout and schematic capture tools (e.g., Virtuoso XL, VXL, or EXL).
• Use of CALIBRE and Hercules verification tools for physical verification.
• Expertise in digital layout including standard cells, memory, and I/O design; analog layout experience is advantageous.
• Strong experience in memory layout and physical verification including LVS, DRC, ERC, antenna, and electromigration checks for CMOS processes.
• Knowledge and experience with floor planning, hierarchical layout, and chip integration.
• Familiarity with Script and SKILL programming is beneficial.
• Solid understanding of memory layout topology and experience with memory compilers is a plus.
• Ability to adapt to new technology reviews to document layout methodologies, flow, and guidelines effectively.
• Self-motivated and capable of working independently as well as collaboratively within a team.