- Experience
- 3+ yrs
- Salary
- —
- Openings
- 1
- Posted
- hace 3 horas
- Work mode
- In office
- Education
- BSEE or MSEE
- Resume
- Required to apply
Where you'll work
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Job description
Job Description and Responsibilities
This role involves the hardware implementation of Image Signal Processing (ISP) algorithms using hardware description languages such as Verilog, SystemVerilog, and potentially SystemC for High Level Synthesis. The candidate will define the ISP hardware architecture considering product features, performance targets, gate count, and power consumption. They are also tasked with verifying logic at both the ISP and broader digital system levels, optimizing the design to minimize gate count and power usage. Close collaboration with the ISP Algorithm team is crucial to drive the overall ISP design process.
Requirements
- A minimum of a Bachelor's or Master’s degree in Electrical Engineering or an equivalent field.
- More than three years of experience in digital design and verification.
- Familiarity with CMOS image sensors and image signal processing technologies.
- Proficient in SystemC/C++, SystemVerilog, and experience with Catapult High-Level Synthesis tools.
- Strong analytical and debugging capabilities.
- Excellent communication and interpersonal skills.
- Result-driven and flexible in adapting to change.
Minimum education
Bachelor's Degree